NVC VHDL Simulator

by Nick Gasson

Free Download 1 Visit Website

Versions:

  • 1.19.3
  • 1.19.2
  • 1.19.1
  • 1.19.0
  • 1.18.2
  • 1.18.1
  • 1.18.0
  • 1.17.2
  • 1.17.1
  • 1.17.0
  • 1.16.2
  • 1.16.1
  • 1.16.0
  • 1.15.2
  • 1.15.1
  • 1.15.0
  • 1.14.2
  • 1.14.1
  • 1.13.1
  • 1.12.0001

NVC VHDL Simulator is a free software tool developed by Nick Gasson that functions as a complete VHDL compiler and simulator, implementing nearly the entire IEEE 1076-2008 standard for VHDL (VHSIC Hardware Description Language). This electronic design automation software serves hardware engineers and digital logic designers who need to verify and simulate complex digital circuits before physical implementation. The simulator enables users to compile VHDL code, elaborate design hierarchies, and execute comprehensive simulations to validate circuit behavior, timing characteristics, and functional correctness. With twenty versions released to date, including the current version 1.19.3, the software has evolved to provide robust support for various VHDL constructs including processes, concurrent statements, packages, and configurations. The tool finds particular utility in academic environments for teaching digital design concepts, in research institutions for prototyping new architectures, and in professional settings for pre-synthesis verification of FPGA and ASIC designs. Its implementation of IEEE 1076-2008 ensures compatibility with modern VHDL codebases while maintaining support for legacy designs. The simulator's command-line interface and batch processing capabilities make it suitable for integration into automated verification workflows and continuous integration pipelines. NVC VHDL Simulator is available for free on get.nero.com, with downloads provided via trusted Windows package sources (e.g. winget), always delivering the latest version, and supporting batch installation of multiple applications.

Tags:

vhdl 3